The invention relates to an assembly for generating a consecutive count including an n-stage binary counter incrementable by counting pulses in successive cycles and an EEPROM in which an item of information representing the count achieved in each case is stored in the pauses between the cycles.
There are applications in which it is necessary to generate a consecutive count, whereby between the individual counting cycles optionally long pauses may exist, on the timeout of which counting is recontinued from the last count. For example, coding systems exist in which the corresponding count is linked to a covert code for generating a so-called signature in making use of a coding algorithm. This signature is then sent to a receiver which in making use of the same count and the covert code known to it, is able to check the received signature as the whether it originates from an authorized sender. Security of transmission is enhanced by making use of the count not recognizable to the outside together with the covert code.
So that the count is incremented from the previous count after a pause it is necessary to store an item of information representing the attained count. When a voltage source is available, storing is no problem since semiconductor memories are available which may serve this purpose. Indeed, even in integrated circuits such a storage may be implemented with no problem as long as a voltage source is always available.
Semiconductor memories also exist in which the stored information is saved when they are disconnected from the power source. Such a memory is termed an electrically erasable programmable read-only memory or, in short, EEPROM, the contents of which is erasable by applying corresponding electrical voltages and enabling information to be written into the individual memory cells.
The disadvantage with an EEPROM is, however, that the manufacturer is able to guarantee only a restricted number of safe storage operations. As soon as this number is exceeded it can no longer be guaranteed that an item of information entered in a memory cell is safely retrievable. One popular value for this number of storage operations is currently 100 000. When the binary numbers to be stored in sequence in such a memory are optional, this maximum number of safe storage operations is very large as long as the contents of each memory cell does not need to be changed in every storage operation. However, the worst case is when a consecutive count needs to be stored since then the contents of the EEPROM memory cell storing the least-significant bit of the count changes on every storage operation. In storing consecutive counts an EEPROM actually becomes unsafe once the cited 100 000 storage cycles is attained. There are applications, however, in which this number of safe storage operations in inadequate.
A general object of the invention is to provide an assembly of the aforementioned kind enabling the number of safe storage operations of an EEPROM to be increased.
In accordance with one aspect of the invention the assembly for generating a consecutive count including an n-stage binary counter incrementable by counting pulses in successive cycles and an EEPROM in which an item of information representing the count achieved in each case is stored in the pauses between the cycles is characterized in that
the EEPROM comprises n+1 memory cells;
a control circuit is provided causing the contents of the nxe2x88x921 stages of the binary counter assigned to the most-significant bits to be stored in the nxe2x88x921 first memory cells of the EEPROM and the contents of the nth or (n+1)th memory cell is changed in alternate cycles;
on commencement of each cycle the contents of the nxe2x88x921 first memory cells of the EEPROM is transferred into the corresponding stages of the binary counter and a bit is written into the nth stage of the binary counter formed by linking the contents of the nth and (n+1)th memory cells of the EEPROM such that the count corresponds to the count attained in the previous cycle, whereby the counting pulse them increments the counter to the next count.
In the assembly in accordance with one aspect of the invention the EEPROM comprises one cell more than the digits of the count generated by the n-stage binary counter, thus making it possible for the control circuit to increment the counter and storage operation so that a cell is no longer available in the EEPROM which changes its contents on each storage operation. It is only the two last cells of the EEPROM that change their status alternately in every second cycle, resulting in the number of safe storage operations being doubled.
Advantageous further embodiments of the invention are characterized in the sub-claims.